Chiplet Architectures Emerge as One Arrow in Industry Quiver of Technologies Extending Compute Performance

As the trend described by Moore’s Law approaches its inevitable end, CAD users and other compute-hungry professionals need the industry to find ways to deliver generation-to-generation improvements in performance.

In the literal sense, the end of Moore’s Law — long and accurately defining the incessant downscaling in silicon-integrated transistor area and cost — is imminent. But focusing energy to push only on the literal meaning of Moore’s Law, rather than its spirit, is a fool’s errand. Because even after its end, technology will continue to advance both performance and price-performance, the true end goals of what Moore’s Law delivered for decades.

Now on the surface, CAD professionals shouldn’t necessarily care about whether Moore’s Law continues or not. But they will care a lot if the industry does not continue to find ways to deliver the generation-to-generation improvements in performance and price-performance that Moore’s Law so elegantly dictated over the past five decades. And really, given their stature as some of the most demanding computing professionals around, they will ultimately be impacted as much as any, should the industry fail to keep up that pace.

The good news is that Moore’s Law or not, the innovative powers of vendors are showing promise to keep progress moving forward, both in the short term and the long. One key component in the short term (at least) is chiplet technology, an approach that leverages the best of silicon at any generation to create higher-performing and better-balanced systems for the most compute-hungry users.

Moore’s Law Was Never the True End

The semantic details are often debated, but Moore’s Law essentially states that transistor counts (per area and cost) double around every two years. It began as an observation based on the early progression of silicon fabrication technology and extended to the current CMOS (complementary metal oxide semiconductor), the technology responsible for virtually all digital ICs (integrated circuits) made for the past 25 years or more. What the law implies — and is often equated with — is a doubling of performance that often comes from the doubling of transistors. The problem, one the industry has seen coming for some time, is that continuing to shrink dimensions at that pace will eventually hit a limit — if not by exacerbating problems like current leakage and thermal dissipation, then eventually by bumping up against quantum effects and atomic dimensions. Opinions vary on how many economically viable denser process nodes are left (each of which can accommodate many more transistors in the same silicon area), and how long it will take to leverage them. But regardless, vendors accept the coming end to Moore’s Law, at least measured in the context of conventional, ubiquitous CMOS technology.

However, too often we dwell on what Moore’s Law is or isn’t — the specific semantics and if it’s alive or dead — rather than the far more important aspect: what it has enabled. Its ability to double performance at the same cost as the previous generation, or to cut cost in half for the same performance — a property no other industry can match — has directly or indirectly given rise to virtually every major technological achievement of the past half-century. Most certainly, it has enabled modern CAD, for without the advances in performance and performance-per-dollar, designers, engineers, and architects wouldn’t have their mission-critical computing tools. Ultimately, the end goal should never be about keeping Moore’s Law alive, but about finding ways to deliver in the future what Moore’s Law delivered in the past. Given that, the industry is re-positioning itself to establish new paths forward to keep a Moore’s Law-ish progression in place — that is, to continue to grow geometrically the value of what the next generation of products and technology can offer.

To do so, vendors are opening up new fronts of attack, open to just about anything (or at least they should be), from relatively conventional evolutionary steps to downright radical departures. Ideas along the evolutionary lines are looking to advance based on our current ecosystem of technologies, materials, and development tools, both hardware and software. What “radical” implies is just about anything else, such as quantum computing that breaks the binary limits, by its nature opening up geometric growth potential via qubit (quantum bit) processing. Though few are likely to bet the farm on it quite yet, quantum computing holds enough promise to justify substantial investment from industry and academia alike. It’s not clear which paths are the most viable, or if some are much more than theory. Despite its promise, quantum computing for example, has some very difficult challenges to overcome — most notably its thermal sensitivity, which currently requires operation at temperatures just a tad north of absolute zero. And regardless of whether quantum computing will eventually evolve into a primary axis to extend computation scaling long term, it’s most certainly not an answer for the short term.

No, in the valley between the peak of CMOS scaling and the next technology peak beyond, the industry needs a compelling answer to bridge forward, and that answer needs to be much more evolutionary and conventional, one compatible with current CMOS-driven design and development infrastructure. The industry is exploring multiple conventional paths, and the answer is shaping up to be not just one tool, but a box full that — in aggregate — can help digital systems like CAD workstations take meaningful steps forward in performance and price-performance, generation to generation.

Chiplet Architectures Pack More Computing Power into the Same Space

While the industry has managed incredible advancements on the back of Moore’s Law, the industry doesn’t have to stagnate with it. For the innovative and adventurous — of which the industry counts many — there are other avenues to explore. One coming to the fore currently is chiplet scaling, an approach being aggressively pursued by both premier providers of high-performance CPUs: Intel and AMD. The chiplet proposition is straightforward: if you can’t stuff more transistors onto a monolithic piece of silicon (or don’t want to, for economic reasons), the other option is to stuff more silicon in the same system area or volume. So rather than simply brute-forcing geometrically higher core counts on the same monolithic die, a chiplet approach aims to package multiple chiplets into a more compact size, consuming less physical area on the circuit board that ultimately populates the computer. That is, if you’re struggling to pack more transistors in the same silicon area, why not change tack and try to pack more silicon chips in the same circuit board area? Though the means is different than on-silicon scaling, the result is similar: more computing power in the same space (assuming proper thermal management, of course).

The preferred way to do that and maintain high performance levels is to use multi-chip packaging. It’s a technique that AMD and Intel are both putting into overdrive, in part to battle the slowing pace of Moore’s Law. It addresses the shorter-term needs, as multi-chip packaging in its general sense is not particularly new and doesn’t require revolutionary thinking or technologies. But the manner in which AMD and Intel are investing in and extending multi-chip packaging is novel, and delivers scaling advantages to help bridge the gap opened up by the demise of Moore’s Law.

Intel’s Foveros. Intel has been attacking the multi-chip packaging front for years, and recently unveiled Foveros technology, representing its most significant and ambitious technology to date. Now being implemented for the first time in a CPU-class product, Foveros pushes beyond conventional interposers and memory to allow clever stacking of two high-performance logic chips, for example CPUs, GPUs, and accelerators (e.g., compute or AI).


A multi-chiplet Foveros 3D package. Image source: Intel.

Foveros goes a step beyond existing multi-chip packaging by stacking two digital logic “chiplets” on top of each other in a scheme that can genuinely be called 3D stacking (and existing memory stacking technologies can be further employed to build up the stack height further). Intel previewed Foveros a while back, combining 10-nm processor/logic chiplets with a 22-nm base die and memory in a remarkably small 12 × 12 × 1 mm package that draws only 2 mW of standby power. Just this summer, Intel unveiled the first product incarnation in mobile-focused Lakefield. With Foveros, Intel can argue that it can double effective transistors per unit surface area and thereby deliver comparable density gains to what Moore’s Law would have achieved in a monolithic die over two years, with a negligible gain in thickness.


Lakefield: Intel’s first Foveros-based product. Image source: Intel.
 

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